This application claims the benefit of the Korean Application No. P2001-57274 filed on Sep. 17, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a ferroelectric memory device capable of improving the sensing margin of a bitline by reducing capacitance between adjacent bitlines and a method for driving the ferroelectric memory.
2. Discussion of the Related Art
Generally, nonvolatile ferroelectric memory, i.e., ferroelectric random access memory (FRAM) has a data processing speed equal to that of dynamic random access memory (DRAM) and retains data even when power is turned off. For this reason, the nonvolatile ferroelectric memory has lately attracted considerable attention as a next generation memory device.
The FRAM and DRAM have similar structures as memory devices, but the FRAM includes a ferroelectric capacitor, which is characteristic of high residual polarization. Such a ferroelectric capacitor permits its data to be retained even when electric field is removed.
FIG. 1 is a conventional characteristic diagram showing a hysteresis loop of a general ferroelectric device. As shown in FIG. 1, the polarization induced by electric field maintains its state at a certain amount (i.e., at the state of xe2x80x9cdxe2x80x9d or xe2x80x9caxe2x80x9d) without being erased due to the presence of residual polarization (or spontaneous polarization) even when electric field is removed. A nonvolatile ferroelectric memory cell can be used as a memory device such that the state of xe2x80x9cdxe2x80x9d or xe2x80x9caxe2x80x9d correspond to the logic value of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d respectively.
FIG. 2 is a schematic diagram showing a unit cell of the general nonvolatile ferroelectric memory device.
As shown in FIG. 2, the nonvolatile ferroelectric memory device includes a bitline B/L formed in one direction, a wordline W/L formed in a direction crossing the bitline B/L, a plate line P/L spaced apart from the wordline W/L in a parallel direction with the wordline W/L, a transistor T1 having a gate electrode connected with the wordline W/L and a source electrode connected with the bitline B/L, and a ferroelectric capacitor FC1 having a first terminal connected with a drain of the transistor T1 and a second terminal connected with the plate line P/L.
A data input and output operation of the aforementioned nonvolatile ferroelectric memory device will be described below.
FIG. 3A is a timing diagram showing a write mode operation of the nonvolatile ferroelectric memory device, and FIG. 3B is a timing diagram showing a read mode operation of nonvolatile ferroelectric memory device.
First, in the write mode operation, a chip enable signal CSBpad applied externally is enabled from high to low. At the same time, if a write enable signal WEBpad is applied from high to low, the write mode operation will start. Subsequently, if address decoding is activated in the write mode operation, a pulse applied to a corresponding wordline W/L will be transited from low to high in order to select a cell.
As described above, during a period of the wordline W/L maintaining at high state, a high signal with a certain period and a low signal with a certain period are sequentially applied to a corresponding plate line P/L. In order to write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline B/L.
In other words, a high signal is applied to the bitline B/L, and if a low signal is applied to the plate line P/L in the period during which the signal applied to the wordline W/L is high, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor FC1.
And a low signal is applied to the bitline B/L, and if the signal applied to the plate line P/L is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor FC1.
An explanation will be given below as to the read mode operation, data of which has been stored in a cell by the write mode operation.
As shown in FIG. 3B, if the chip enable signal CSBpad applied externally is enabled from high to low, all of bitlines B/L will be equipotential to a low voltage by an equalizer signal EQ before the corresponding wordline W/L is selected.
The corresponding bitline B/L becomes inactive. Then an address is decoded, and the corresponding wordline W/L is transited from low to high according to the decoded address in order to select the corresponding cell.
Subsequently, a high signal is applied to the plate line P/L of the selected cell in order to destroy the data corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric memory. If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, the corresponding data will not be destroyed.
As described above, the data destroyed or non-destroyed are output as values different with each other according to the principle of hysteresis loop, and thereby the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is sensed by a sensing amplifier. In other words, as shown in the hysteresis loop of FIG. 1, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is changed to the xe2x80x9cfxe2x80x9d state, whereas if the data is not destroyed, the xe2x80x9caxe2x80x9d state is changed to the xe2x80x9cfxe2x80x9d state.
Thus, if the sensing amplifier is enabled after a constant time elapses, the logic value xe2x80x9c1xe2x80x9d is output in the case where the data is destroyed, while the logic value xe2x80x9c0xe2x80x9d is output in case where the data is not destroyed.
As described above, after the data is output by the sensing amplifier, it should be recovered to its original data, the plate line P/L disabled from high to low during the state in which a high signal is applied to the corresponding wordline W/L.
A conventional ferroelectric memory device and a method for driving the same will be described below with reference to the accompanying drawings.
FIG. 4 is a circuit diagram showing the conventional nonvolatile ferroelectric memory element.
As shown in FIG. 4, a unit cell of the conventional nonvolatile ferroelectric memory element formed in the row direction includes a first split wordline SW1 and a second split word line SW2 which are parallel with each other, a first bitline BL1 and a second bitline BL2 formed crossing the first and the second split wordlines SW1 and SW2, a first transistor T1 having a gate connected to the first split wordline SWL1 and a drain connected to the first bitline BL1, a first ferroelectric capacitor FC1 connected between a source of the first transistor T1 and the second split wordline SWL2, a second transistor T2 having a gate connected to the second split wordline SWL2 and a drain connected to the second bitline BL2, and a second ferroelectric capacitor FC2 connected between a source of the second transistor T2 and the first split wordline SWL1.
FIG. 5 is another circuit diagram showing the conventional nonvolatile ferroelectric memory device.
As shown in FIG. 5, the conventional nonvolatile ferroelectric memory device includes a plurality of pairs of split word lines having a pair of a first and a second split wordlines SWL1, SWL2 in the row direction, a plurality of pairs of bitlines having a pair of adjacent two bitlines BL1, BL2 in a direction crossing the pairs of wordlines SW1, SW2, a plurality of sensing amplifiers SA located between the pair of bitlines BL1, BL2 and serving to sense data received via both the bitlines BL1, BL2 and transmit the data to a data line DL or a data bar line /DL.
Here, a sensing amplifier enabling part (not shown) outputs a sensing amplifier enable signal SEN to enable the sensing amplifiers, a selection switching part CS switches the bitlines, and additionally, the data lines are selectively formed.
FIG. 6 is a timing diagram showing an operation of the conventional nonvolatile ferroelectric memory element.
A period T0 shown in FIG. 6 prior to a period during which the first split wordline SWL1 and the second split wordline SWL2 are enabled to high, is precharged to a constant level for all the bitlines. Then, during a T1 period, both the first split wordline SWL1 and the second split wordline SWL2 are high, so that the data of ferroelectric capacitor is transmitted to a bitline BL so that the level of the bitline BL is changed.
At this time, since the ferroelectric capacitor stored as logic xe2x80x9c1xe2x80x9d is subjected to the opposite polarities of electric fields on the bitline and wordline, the polarity of the ferroelectric memory element is destroyed, and high current is generated and accordingly high voltage is induced to the bitline.
On the contrary, since the ferroelectric capacitor stored as logic xe2x80x9c0xe2x80x9d is subjected to the same polarities of electric fields on the bitline and wordline, the polarity of ferroelectric memory element is not destroyed, and low current is generated and accordingly low voltage is induced to the bitline.
When a cell data is loaded sufficiently on the bitline, the sensing amplifier enable signal SEN is transited to high in order to enable the sensing amplifier, and the level of the bitline is amplified. However, since the data of logic xe2x80x9c1xe2x80x9d in the cell which has been destroyed cannot be recovered at the state in which both the first split wordline SW1 and the second split wordline SW2 are high, it should be restored in the following periods T2, T3.
Then, during the period T2 of the first split wordline SWL1 being transited to a low level and the second split wordline SWL2 maintaining a high level, the second transistor T2 is turned on.
At this time, if the corresponding bitline is at a high level, high data is transmitted to an electrode of the second ferroelectric capacitor FC2, it will be restored to the logic xe2x80x9c1xe2x80x9d between a low level of the first split wordline SWL1 and a high level of the bit line.
Then, during the period T3 of the first split wordline SWL1 being transited to high again and the second split wordline SWL2 is transited to low, the first transistor T1 is turned on.
At this time, if the corresponding bitline is at a high level, a high data will be transmitted to an electrode of the first ferroelectric capacitor FC1, and the logic xe2x80x9c1xe2x80x9d is restored between a low level of the second split wordline SWL2 and a high level of the bit line.
Then, the T4 period is a precharge period during which a next cycle operation is prepared.
FIG. 7 is a diagram showing a folded bitline cell array for the conventional nonvolatile ferroelectric memory device.
The conventional 1T/1C FRAM unit cell is the 1T/1C having one transistor and one capacitor, similar to DRAM in structure.
As shown FIG. 7, the conventional 1T/1C FRAM includes a plurality of wordlines WL1, WL2 arranged parallel with each other, a plurality of plate lines PL1, PL2 arranged parallel to the wordlines WL1, WL2 between each pair of the wordlines WL1, WL2, and a plurality of bitlines BL1, BL2, BL3, BL4, . . . arranged parallel with each other and perpendicular to the wordlines WL1, WL2 and the plate lines PL1, PL2.
The conventional 1T/1C FRAM also includes a plurality of unit cells are arranged in a folded type. In other words, each unit cell includes a transistor having a gate electrode connected to the wordline WL1, a source electrode connected to the adjacent bitline BL1, a drain electrode connected to a first electrode of a ferroelectric capacitor. A second electrode of the ferroelectric capacitor is connected to the adjacent plate line PL1.
However, a gate electrode of another transistor included in the unit cell is connected to the wordline WL2, a source electrode of the transistor is connected to the adjacent bitline BL2, a drain electrode of the transistor is connected to a first electrode of a ferroelectric capacitor, and a second electrode of the ferroelectric capacitor is connected to the adjacent plate line PL2.
Here, the respective cell arrays include cells in row and columns directions, and the cells in the row direction are arranged per every other column, and similarly, the cells in the column direction are arranged per every other row.
However, as for a bitline cell array of the conventional ferroelectric memory device, when the wordline WL1 and the plate line PL1 are enabled, only the cells connected with the odd numbers of the bitlines BL1, BL3 or the even numbers of the bitlines BL2, BL4 are selected, and the even numbers of the bitlines BL2, BL4 or the odd numbers of bitlines BL1, BL3, which are not selected, will be regarded as reference lines or driver lines.
FIG. 8 is a timing diagram showing the operation of a folded bitline cell array for the conventional ferroelectric memory device.
As shown in FIG. 8, a chip enable signal ICE is disabled to low during a period b1. During a period b2, both a wordlines WL and a plate lines PL are enabled to high and cell data are loaded on the bitlines BL. Accordingly, high or low sensing data will appear on the bitlines BL.
During a period b3, the sensing amplifier enable signal SAE is enabled from low to high, and the bitline BL data is amplified by the sensing amplifier enable signal SAE. During a period b4, the logic xe2x80x9c0xe2x80x9d is written to the cell, and the logic xe2x80x9c1xe2x80x9d is written to the cell during a period b5. The periods b4 and b5 are defined as the cell data store or write periods. In other words, they are periods during which the bitline data are newly written or rewritten to the cell in the write or read mode. During a period b6, the bitlines BL and others are precharged for a next cycle.
However, the aforementioned conventional ferroelectric memory device and a method for driving the conventional ferroelectric memory device have the following problems. That is, the capacitance between adjacent bitlines is increased, and as a result the bitline sensing margin is decreased.
Accordingly, the present invention is directed to a ferroelectric memory device and a method for driving the same that substantially obviates the conventional problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a ferroelectric memory device and a method for driving the same in which hierarchical structure is adopted for bitlines, thereby reducing the capacitance in order to improve the sensing margin of bitlines.
In accordance with the purpose of the invention to achieve this object, a ferroelectric memory device includes a plurality of wordlines and a plurality of plate lines, the wordlines and the plate lines being alternately formed at regular intervals in one direction; a plurality of sub bitlines and a plurality of main bitlines, the sub bitlines and the main bitlines alternately formed at regular intervals to cross the wordlines and the plate lines; a plurality of sub cell arrays connected with the wordlines, the sub bitlines and the plate lines, having cells in directions defined by a plurality of rows and columns, the cells in the direction of the rows being arranged every two columns and the cells in the direction of the columns being arranged every two rows, respectively; and switching elements each operating between one of the sub bitlines and one of the main bitlines by an externally applied bitline switch signal of a constant pulse type to selectively connect the sub bitline with the main bitline.
Also, in accordance with the purpose of the invention to achieve this object, a method for driving a ferroelectric memory device includes the steps of selecting only cells connected with odd numbers of bitlines or even numbers of bitlines by activating a corresponding bitline switching signal to connect a main bitline with an adjacent sub bitline when a wordline and a plate line are enabled, and using the even numbers of bitlines or the odd numbers of bitlines, which have not been selected, as the reference line, the ferroelectric memory device includes a plurality of wordlines and plate lines formed alternatively each other to have regular spacing in one direction, a plurality of sub bitlines and main bitlines formed alternatively each other to have regular spacing in a direction to cross the wordlines and plate lines, cells connected with the wordlines, sub bitlines and plate lines in directions defined by a plurality of rows and columns, a plurality of sub cell arrays having the cells in the direction of the rows to be arranged every other column respectively as well as the cells in the direction of the columns to be arranged every other row respectively, and switching elements each connecting one of the sub bitline with one of the main bitline selectively between the sub bitline and the main bitline by operation of the bitline switch signal applied externally in a constant pulse type.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed,